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Huawei Ascend 950PR Matrix calculations only H100 of the speed,DeepSeek is squeezing performance out of the software
According to a Beating AI news brief, last year,DeepSeek tried using Huawei Ascend chips to train R2, but even with Huawei engineers providing on-site assistance, it still failed to run successfully. Problems existed with chip stability, cross-chip communication, and software support. This year, the two sides continued to deepen their cooperation.September At the end of the year,DeepSeek publicly released six sets of Ascend adaptation code;October there were also reports that Huawei was adjusting its next-generation chip design according to the model requirements of DeepSeek.
The semiconductor research firm SemiAnalysis recently published measured results for Ascend 950PR. Researchers selected 1055 groups of matrix calculations commonly used by large models and found that Huawei's own low-level programs had already enabled 950PR to achieve 86%of its attainable computing power, higher than Nvidia H100's 75.5%. However, the actual computation speed was still only H100 of 43%, and compared with the newer B300 it was only 21%. These results did not yet use the operators newly ported by DeepSeek.DeepSeek is reducing data transfers and waiting time through software. For example, when running attention calculations, two data sets that originally had to be read separately can be retrieved at once after FlashMLA adjusted the storage method. Another tool,TileLang, enables the chip to calculate while preloading the next batch of data. SemiAnalysis measured that automatic scheduling reduced the time required for some small computational tasks by up to approximately 40%。DeepSeek also ported DeepEP, which handles communication among MoE experts, but communication and computation still compete for memory bandwidth, and Huawei plans to continue improving the firmware.
The 950PR tested this time mainly targets inference input processing, while DeepSeek is preparing to use 950DT for large-scale pretraining as early as the end of the year. The two sides had previously conducted testing at the -chip scale, but enabling tens of thousands of chips to continuously complete one round of large-model training will require resolving more complex coordination and stability issues.
Original link https://m.theblockbeats.info/flash/373937