TSMC A14 process plans to reduce the SRAM cell area to 0.017 square micrometers or less

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TSMC A14 process will SRAM shrink the cell area to 0.017 square micrometers or less, restarting scaling after 8 years

According to BlockBeats,October 26, TSMC plans to reduce the high-density 2028 process, targeted for mass production in A14, 6T SRAM(static random-access memory) bit-cell area to 0.017 square micrometers or less, breaking the long-standing stagnation at approximately 2020 since the N5 process, where it has remained at approximately 0.021 square micrometers.

The report said TSMC is expected to announce the relevant research results at the end of the year. Based on currently disclosed data, the A14 process's SRAM cell area is expected to lead Intel's 18A process; the latter previously disclosed a high-density SRAM cell area of 0.021 square micrometers. As Samsung has not yet disclosed the specific SRAM cell size of its latest process, direct comparison is temporarily difficult.SRAM is CPU、GPU and AI key storage components used for high-speed cache inside accelerator chips. Reducing cell area allows more cache to fit within the same chip area, helping alleviate the data-access bottleneck of AI chips and improve performance and energy efficiency.

TSMC said the A14 process, compared with the N2 process, targets a performance increase of 10%to 15%, a power-consumption reduction of 25%to 30%, and an approximately 20%increase in chip density. The process is currently advancing toward the mass-production target for 2028, but final yield, cost, and customer adoption remain to be confirmed.

Original link https://m.theblockbeats.info/flash/373739

Key points

TSMC plans, in the 2028 process targeted for mass production in A14, to reduce the high-density 6T SRAM bit-cell area to 0.017 square micrometers or less.
Reports say TSMC is expected to announce the relevant research results at the end of the year.
Intel 18A process previously disclosed a high-density SRAM cell area of 0.021 square micrometers.
Samsung has not yet disclosed the specific SRAM cell size of its latest process.
TSMC said that,A14 compared with N2 the target is a performance increase of 10%to 15%, a power-consumption reduction of 25%to 30%, and an approximately increase in chip density 20%。
A14 The process is currently advancing toward the 2028 mass-production target.

AI-assisted interpretation

The following is analysis, separate from reported facts. Verify important claims independently.

SRAM is CPU、GPU and AI storage components used for high-speed cache inside accelerator chips. Smaller cell areas theoretically allow more cache to fit on a chip of the same size.

Why it matters to readers

If the relevant metrics are ultimately achieved,A14 may lead in SRAM area metrics over Intel's 18A, and help improve cache capacity, performance, and energy efficiency.

This relates to whether AI chips and processors can fit more high-speed cache within a limited area, but research targets do not mean that mass production or customer adoption has already occurred.

Risks and unknowns

A14 final SRAM cell area remains subject to confirmation by the research results.
Final yield, cost, and customer adoption remain to be confirmed.
2028 mass-production schedule remains unconfirmed.
Samsung has not yet disclosed the specific SRAM cell size of its latest process, making direct comparison temporarily difficult.

TSMC A14 process plans to reduce the SRAM cell area to 0.017 square micrometers or less

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